In the semiconductor industry, the use of electrostatic discharge protection (ESD) circuits is known. ESD circuits ensure that integrated semiconductor devices are not destroyed by static electricity during routine post-manufacture processes. However, current and foreseeable trends in the semiconductor industry are adversely impacting the effectiveness of known ESD circuits.
For instance, the use of heavily doped epitaxial (epi) substrates prevents metal oxide semiconductor (MOS) field effect transistors (FETs) and thick field oxide (TFO) devices from acting as current shunting devices. In normal use, a heavily doped substrate is desirable. Such a substrate reduces the undesirable occurrence of "latch-up." During latch-up, two parasitic bipolar transistors formed by two complimentary MOSFETs create a feedback loop. In the feedback loop, the base of the first parasitic bipolar device is also the collector of the second device. Conversely, the base of the second device is the collector of the first device. When both of these transistors are conducting, large amounts of current can flow between two power supplies. A high current event applied to one of the terminals of the two transistors can cause the two parasitic transistors to conduct. A heavily doped epitaxial substrate acts to break the feedback loop by grounding the substrate and, hence, the base of one device and the collector of the other.
The use of salicide bonding layers to reduce sheet resistivity (rho) also decreases the effectiveness of known ESD circuits. Here, several MOSFETs or several fmgers forming a single MOSFET act as a parasitic bipolar device to provide ESD protection. Such an ESD device relies upon the "snap-back" current-voltage characteristics of a parasitic bipolar transistor. There, a current begins to flow through a bipolar transistor at a certain collector-to-emitter voltage, V.sub.t1. Thereafter, the collector-to-emitter voltage decreases as the current increases, "snapping-back" from V.sub.t1. Later, the trend reverses, causing the collector-to-emitter voltage to rise as the current also rises. Eventually, the bipolar transistor fails at another particular collector-to-emitter voltage, V.sub.t2. The low resistance of the salicide layer can cause the ultimate breakdown voltage, V.sub.t2 to be lower than the initial voltage, V.sub.t1. Such a relationship causes the first MOSFET or first finger of the MOSFET to breakdown at a voltage less than the voltage at which the second MOSFET turns on. Consequently, the protection provided by the group of MOSFETs is no greater than the protection provided by a single MOSFET.
Some known ESD circuits rely on the inherent capacitance between the voltage rails of a integrated circuit to shunt excess energy applied to one voltage rail to the other. This strategy minimizes the total number of devices necessary to provide protection. However, this strategy also fails as the capacitance of the integrated circuit drops. Consequently, one ESD circuit designed for a particular integrated circuit may not be sufficient for another circuit.
Die reduction is one of the overriding trends in the semiconductor industry. As integrated circuits shrink, the area allocated to ESD circuits shrinks. Typically, an ESD circuit is placed below an input, output, or I/O pin which the circuit protects. This area is rapidly becoming inadequate to host such circuits.
Other known ESD circuits rely on diode strings to shunt power. Unfortunately, these diode strings leak current at elevated temperatures. Furthermore, each diode's leakage increases with its temperature. Another trend in the semiconductor industry is to design and manufacture integrated circuits that consume as little current as possible and that are suitable for wide usage. Both of these goals is adversely impacted by leaky designs that are limited by environmental concerns.